74LVQ74SC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Set(Preset) and Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 125MHz |
| Family | LVQ |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 14ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| fmax-Min | 95 MHz |
| Length | 8.65mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LVQ74SC Overview
The package is in the form of 14-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. It is configured with Differentialas an output. The trigger configured with it uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates at a voltage of 2V~3.6V. -40°C~85°C TAis the operating temperature. D-Typedescribes this flip flop. FPGAs belonging to the 74LVQseries contain this type of chip. You should not exceed 125MHzin the output frequency of the device. In total, it contains 2 elements. T flip flop consumes 20μA quiescent energy. Terminations are 14. The D flip flop is powered by a voltage of 2.7V . This T flip flop has a capacitance of 4.5pF farads at the input. In this case, the D flip flop belongs to the LVQfamily. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be kept above 2V.
74LVQ74SC Features
Tube package
74LVQ series
74LVQ74SC Applications
There are a lot of Rochester Electronics, LLC 74LVQ74SC Flip Flops applications.
- Divide a clock signal by 2 or 4
- Supports Live Insertion
- Clock pulse
- Shift Registers
- Latch
- Data Synchronizers
- Storage Registers
- Single Up Count-Control Line
- Computing
- Communications
