74LVT16374ADL,112
| Parameters | |
|---|---|
| Input Capacitance | 3pF |
| Power Supply Current-Max (ICC) | 6mA |
| Number of Output Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Width | 7.5mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-BSSOP (0.295, 7.50mm Width) |
| Number of Pins | 48 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 48 |
| Type | D-Type |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT16374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Number of Bits | 16 |
| Clock Frequency | 150MHz |
| Propagation Delay | 3 ns |
| Quiescent Current | 4mA |
| Turn On Delay Time | 3 ns |
| Family | LVT |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 120μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Max Propagation Delay @ V, Max CL | 5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
74LVT16374ADL,112 Overview
The flip flop is packaged in a case of 48-BSSOP (0.295, 7.50mm Width). There is an embedded version in the package Tube. There is a Tri-State, Non-Invertedoutput configured with it. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 2.7V~3.6V. Temperature is set to -40°C~85°C TA. There is D-Type type of electronic flip flop associated with this device. In FPGA terms, D flip flop is a type of 74LVTseries FPGA. You should not exceed 150MHzin the output frequency of the device. The element count is 2 . As a result, it consumes 120μA quiescent current. A total of 48 terminations have been made. JK flip flop belongs to 74LVT16374 family. A voltage of 3.3V is used as the power supply for this D latch. Its input capacitance is 3pFfarads. This D flip flop belongs to the family of LVT. There is an electronic part mounted in the way of Surface Mount. The electronic flip flop is designed with pins 48. This device has the clock edge trigger type of Positive Edge. There are 16bits in its design. It reaches the maximum supply voltage (Vsup) at 3.6V. The flip flop has 2embedded ports. In order to achieve high efficiency, the supply voltage should be maintained at 3.3V. In order for the chip to function, it has 8output lines. It consumes a total of 4mA quiescent current at any given time.
74LVT16374ADL,112 Features
Tube package
74LVT series
48 pins
16 Bits
74LVT16374ADL,112 Applications
There are a lot of Nexperia USA Inc. 74LVT16374ADL,112 Flip Flops applications.
- Data storage
- CMOS Process
- Load Control
- Frequency division
- Data Synchronizers
- Shift Registers
- Buffered Clock
- Power down protection
- Safety Clamp
- Communications
