74LVT16374MTD
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 day ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Number of Pins | 48 |
| Weight | 421mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 48 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74LVT16374 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 2 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Output Current | 64mA |
| Clock Frequency | 160MHz |
| Propagation Delay | 5.4 ns |
| Turn On Delay Time | 4.5 ns |
| Family | LVT |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Number of Output Lines | 16 |
| Clock Edge Trigger Type | Positive Edge |
| Width | 6.1mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVT16374MTD Overview
In the form of 48-TFSOP (0.240, 6.10mm Width), it has been packaged. You can find it in the Tubepackage. Currently, the output is configured to use Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates at a voltage of 2.7V~3.6V. -40°C~85°C TAis the operating temperature. This D latch has the type D-Type. JK flip flop is a part of the 74LVTseries of FPGAs. Its output frequency should not exceed 160MHz. A total of 2elements are present in it. It consumes 190μA of quiescent There are 48 terminations,It is a member of the 74LVT16374 family. A voltage of 3.3V is used as the power supply for this D latch. Input capacitance of this device is 4pF farads. The electronic device belongs to the LVTfamily. There is an electronic component mounted in the way of Surface Mount. The 48pins are designed into the board. This device exhibits a clock edge trigger type of Positive Edge. This part is included in FF/Latches. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). There are 2 ports embedded in the flip flops. If high efficiency is desired, the supply voltage should be kept at 3.3V. With an output current of 64mA, this device offers maximum design flexibility. It operates with 16 output lines.
74LVT16374MTD Features
Tube package
74LVT series
48 pins
74LVT16374MTD Applications
There are a lot of ON Semiconductor 74LVT16374MTD Flip Flops applications.
- Buffer registers
- Bounce elimination switch
- CMOS Process
- Guaranteed simultaneous switching noise level
- Memory
- ESD performance
- Matched Rise and Fall
- Computing
- Control circuits
- Modulo – n – counter
