74LVT273DB,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.9 ns |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVT273DB,112 Overview
20-SSOP (0.209, 5.30mm Width)is the packaging method. The Tubepackage contains it. In the configuration, Non-Invertedis used as the output. There is a trigger configured with Positive Edge. This electronic part is mounted in the way of Surface Mount. The supply voltage is set to 2.7V~3.6V. In this case, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. It is a type of FPGA belonging to the 74LVT series. A frequency of 150MHzshould be the maximum output frequency. In total, it contains 1 elements. There is 190μA quiescent consumption. There are 20 terminations,Members of the 74LVT273family make up this object. The power supply voltage is 3.3V. A 4pFfarad input capacitance is provided by this T flip flop. This D flip flop belongs to the family of LVT. It is part of the FF/Latchesbase part number family. It reaches the maximum supply voltage (Vsup) at 3.6V. For normal operation, the supply voltage (Vsup) should be kept above 2.7V. The power supply is 3.3V.
74LVT273DB,112 Features
Tube package
74LVT series
3.3V power supplies
74LVT273DB,112 Applications
There are a lot of NXP USA Inc. 74LVT273DB,112 Flip Flops applications.
- ESD performance
- Frequency Divider circuits
- Safety Clamp
- Storage Registers
- Frequency Dividers
- Consumer
- Data storage
- Bounce elimination switch
- Frequency division
- Differential Individual
