74LVT273PW,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.9 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVT273PW,118 Overview
The item is packaged in 20-TSSOP (0.173, 4.40mm Width)cases. It is included in the package Tape & Reel (TR). It is configured with Non-Invertedas an output. There is a trigger configured with Positive Edge. Surface Mountis occupied by this electronic component. A voltage of 2.7V~3.6Vis used as the supply voltage. A temperature of -40°C~85°C TAis used in the operation. This electronic flip flop is of type D-Type. JK flip flop is a part of the 74LVTseries of FPGAs. This D flip flop should not have a frequency greater than 150MHz. D latch consists of 1 elements. T flip flop consumes 190μA quiescent energy. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The 74LVT273 family contains it. It is powered from a supply voltage of 3.3V. This T flip flop has a capacitance of 4pF farads at the input. An electronic device belonging to the family LVTcan be found here. It is part of the FF/Latchesbase part number family. It reaches the maximum supply voltage (Vsup) at 3.6V. Keeping the supply voltage (Vsup) above 2.7V is necessary for normal operation. As a result of its reliable performance, this T flip flop is suitable for TAPE AND REEL. It operates from 3.3V power supplies.
74LVT273PW,118 Features
Tape & Reel (TR) package
74LVT series
3.3V power supplies
74LVT273PW,118 Applications
There are a lot of NXP USA Inc. 74LVT273PW,118 Flip Flops applications.
- Pattern generators
- Dynamic threshold performance
- Patented noise
- Parallel data storage
- Supports Live Insertion
- ATE
- Counters
- Common Clocks
- Clock pulse
- Shift Registers
