74LVT374D,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.5 ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LVT374D,112 Overview
It is packaged in the way of 20-SOIC (0.295, 7.50mm Width). As part of the package Tube, it is embedded. Currently, the output is configured to use Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. Currently, the operating temperature is -40°C~85°C TA. It is an electronic flip flop with the type D-Type. It is a type of FPGA belonging to the 74LVT series. A frequency of 200MHzshould be the maximum output frequency. D latch consists of 1 elements. It consumes 190μA of quiescent current without being affected by external factors. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LVT374 family contains it. An input voltage of 3.3Vpowers the D latch. A 4pFfarad input capacitance is provided by this T flip flop. Devices in the LVTfamily are electronic devices. This device is part of the FF/Latchesbase part number family. Vsup reaches 3.6V, the maximal supply voltage. It is imperative that the supply voltage (Vsup) is maintained above 2.7Vin order to ensure normal operation. The D latch runs on a voltage of 3.3V volts. This flip flop has a total of 2ports.
74LVT374D,112 Features
Tube package
74LVT series
3.3V power supplies
74LVT374D,112 Applications
There are a lot of NXP USA Inc. 74LVT374D,112 Flip Flops applications.
- Differential Individual
- Asynchronous counter
- Counters
- ESD protection
- Reduced system switching noise
- Automotive
- Dynamic threshold performance
- Frequency Dividers
- Supports Live Insertion
- Event Detectors
