74LVT374WM
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Height Seated (Max) | 2.642mm |
| Width | 7.493mm |
| RoHS Status | ROHS3 Compliant |
74LVT374WM Overview
The flip flop is packaged in 20-SOIC (0.295, 7.50mm Width). D flip flop is embedded in the Tube package. T flip flop is configured with an output of Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. This electronic part is mounted in the way of Surface Mount. A 2.7V~3.6Vsupply voltage is required for it to operate. In the operating environment, the temperature is -40°C~85°C TA. The type of this D latch is D-Type. The FPGA belongs to the 74LVT series. It should not exceed 160MHzin its output frequency. D latch consists of 1 elements. This process consumes 190μA quiescents. Terminations are 20. A voltage of 3.3V is used to power it. This T flip flop has a capacitance of 3pF farads at the input. An electronic device belonging to the family LVTcan be found here. As soon as 3.6Vis reached, Vsup reaches its maximum value. The supply voltage (Vsup) should be maintained above 2.7V for normal operation. There are 2 ports embedded in the flip flops.
74LVT374WM Features
Tube package
74LVT series
74LVT374WM Applications
There are a lot of Rochester Electronics, LLC 74LVT374WM Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Single Up Count-Control Line
- Computing
- Computers
- Memory
- Balanced 24 mA output drivers
- Storage registers
- Balanced Propagation Delays
- Single Down Count-Control Line
- Automotive
