74LVT74DB,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT74 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Clock Frequency | 345MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 1mA |
| Current - Output High, Low | 20mA 32mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVT74DB,118 Overview
It is packaged in the way of 14-SSOP (0.209, 5.30mm Width). It is included in the package Tape & Reel (TR). Currently, the output is configured to use Differential. The trigger configured with it uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2.7V~3.6V volts. A temperature of -40°C~85°C TAis considered to be the operating temperature. There is D-Type type of electronic flip flop associated with this device. In terms of FPGAs, it belongs to the 74LVT series. A frequency of 345MHzshould not be exceeded by its output. A total of 2elements are contained within it. T flip flop consumes 1mA quiescent energy. Currently, there are 14 terminations. The 74LVT74 family contains it. The D flip flop is powered by a voltage of 3.3V . A 3pFfarad input capacitance is provided by this T flip flop. In this case, the D flip flop belongs to the LVTfamily. This part is included in FF/Latches. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. As a result of its reliability, this D flip flop is ideally suited for TAPE AND REEL. It operates from 3.3V power supplies.
74LVT74DB,118 Features
Tape & Reel (TR) package
74LVT series
3.3V power supplies
74LVT74DB,118 Applications
There are a lot of NXP USA Inc. 74LVT74DB,118 Flip Flops applications.
- Single Down Count-Control Line
- Data storage
- Memory
- Buffered Clock
- Latch-up performance
- Latch
- Safety Clamp
- Buffer registers
- Convert a momentary switch to a toggle switch
- Set-reset capability
