74LVTH273SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.5 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVTH273SJX Overview
As a result, it is packaged as 20-SOIC (0.209, 5.30mm Width). As part of the package Tape & Reel (TR), it is embedded. T flip flop uses Non-Invertedas the output. In the configuration of the trigger, Positive Edgeis used. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2.7V~3.6V volts. A temperature of -40°C~85°C TAis used in the operation. There is D-Type type of electronic flip flop associated with this device. This type of FPGA is a part of the 74LVTH series. This D flip flop should not have a frequency greater than 150MHz. In total, there are 1 elements. There is 190μA quiescent consumption. There have been 20 terminations. Power is provided by a 3V supply. The input capacitance of this JK flip flopis 3pF farads. It is a member of the LVTfamily of D flip flop. Vsup reaches 3.6V, the maximal supply voltage. The supply voltage (Vsup) should be maintained above 2.7V for normal operation.
74LVTH273SJX Features
Tape & Reel (TR) package
74LVTH series
74LVTH273SJX Applications
There are a lot of Rochester Electronics, LLC 74LVTH273SJX Flip Flops applications.
- Balanced 24 mA output drivers
- ATE
- Dynamic threshold performance
- Buffer registers
- Computing
- Control circuits
- Safety Clamp
- Cold spare funcion
- ESCC
- Single Up Count-Control Line
