74LVTH273WM
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.5 ns |
| Height Seated (Max) | 2.642mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LVTH273WM Overview
The package is in the form of 20-SOIC (0.295, 7.50mm Width). D flip flop is included in the Tubepackage. The output it is configured with uses Non-Inverted. This trigger is configured to use Positive Edge. It is mounted in the way of Surface Mount. The supply voltage is set to 2.7V~3.6V. In the operating environment, the temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. JK flip flop belongs to the 74LVTHseries of FPGAs. It should not exceed 150MHzin terms of its output frequency. In total, it contains 1 elements. There is a consumption of 190μAof quiescent energy. 20terminations have occurred. Power is provided by a 3V supply. Its input capacitance is 3pFfarads. It is a member of the LVTfamily of D flip flop. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. For normal operation, the supply voltage (Vsup) should be kept above 2.7V.
74LVTH273WM Features
Tube package
74LVTH series
74LVTH273WM Applications
There are a lot of Rochester Electronics, LLC 74LVTH273WM Flip Flops applications.
- Test & Measurement
- QML qualified product
- Power down protection
- Latch
- Asynchronous counter
- Common Clocks
- 2 – Bit synchronous counter
- Registers
- Differential Individual
- Shift registers
