74LVTH374SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVTH374SJX Overview
As a result, it is packaged as 20-SOIC (0.209, 5.30mm Width). As part of the package Tape & Reel (TR), it is embedded. This output is configured with Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. The electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of 2.7V~3.6V. The operating temperature is -40°C~85°C TA. A flip flop of this type is classified as a D-Type. The 74LVTHseries comprises this type of FPGA. You should not exceed 160MHzin the output frequency of the device. D latch consists of 1 elements. As a result, it consumes 190μA of quiescent current without being affected by external factors. There are 20 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Power is supplied from a voltage of 3.3V volts. Its input capacitance is 3pFfarads. A device of this type belongs to the family of LVT. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. The supply voltage (Vsup) should be kept above 2.7V for normal operation. A D flip flop with 2embedded ports is available.
74LVTH374SJX Features
Tape & Reel (TR) package
74LVTH series
74LVTH374SJX Applications
There are a lot of Rochester Electronics, LLC 74LVTH374SJX Flip Flops applications.
- Computers
- Balanced Propagation Delays
- Data storage
- QML qualified product
- Single Up Count-Control Line
- Safety Clamp
- Event Detectors
- EMI reduction circuitry
- Patented noise
- Dynamic threshold performance
