74LVTH374WM
| Parameters | |
|---|---|
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Height Seated (Max) | 2.642mm |
| Width | 7.493mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
74LVTH374WM Overview
The flip flop is packaged in a case of 20-SOIC (0.295, 7.50mm Width). D flip flop is included in the Tubepackage. There is a Tri-State, Non-Invertedoutput configured with it. The trigger configured with it uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. With a supply voltage of 2.7V~3.6V volts, it operates. Temperature is set to -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. In terms of FPGAs, it belongs to the 74LVTH series. A frequency of 160MHzshould be the maximum output frequency. D latch consists of 1 elements. T flip flop consumes 190μA quiescent energy. There are 20 terminations,An input voltage of 3.3Vpowers the D latch. The input capacitance of this JK flip flopis 3pF farads. In this case, the D flip flop belongs to the LVTfamily. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. The supply voltage (Vsup) should be kept above 2.7V for normal operation. This flip flop has a total of 2ports.
74LVTH374WM Features
Tube package
74LVTH series
74LVTH374WM Applications
There are a lot of Rochester Electronics, LLC 74LVTH374WM Flip Flops applications.
- Modulo – n – counter
- Parallel data storage
- Buffer registers
- Data storage
- Bounce elimination switch
- ESD performance
- 2 – Bit synchronous counter
- EMI reduction circuitry
- Data transfer
- Memory
