74LVTH374WMX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Height Seated (Max) | 2.642mm |
| Width | 7.493mm |
| RoHS Status | ROHS3 Compliant |
74LVTH374WMX Overview
The package is in the form of 20-SOIC (0.295, 7.50mm Width). D flip flop is included in the Tape & Reel (TR)package. The output it is configured with uses Tri-State, Non-Inverted. The trigger configured with it uses Positive Edge. Surface Mountmounts this electrical part. With a supply voltage of 2.7V~3.6V volts, it operates. Temperature is set to -40°C~85°C TA. The type of this D latch is D-Type. In this case, it is a type of FPGA belonging to the 74LVTH series. You should not exceed 160MHzin its output frequency. The list contains 1 elements. It consumes 190μA of quiescent Terminations are 20. A voltage of 3.3V is used as the power supply for this D latch. Its input capacitance is 3pFfarads. Electronic devices of this type belong to the LVTfamily. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. A normal operating voltage (Vsup) should remain above 2.7V. The D flip flop has no ports embedded.
74LVTH374WMX Features
Tape & Reel (TR) package
74LVTH series
74LVTH374WMX Applications
There are a lot of Rochester Electronics, LLC 74LVTH374WMX Flip Flops applications.
- Clock pulse
- High Performance Logic for test systems
- Buffered Clock
- Registers
- Test & Measurement
- ESD protection
- Balanced Propagation Delays
- Modulo – n – counter
- CMOS Process
- Single Up Count-Control Line
