74LVX273SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 90MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 4mA 4mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 14.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 24 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74LVX273SJX Overview
The flip flop is packaged in a case of 20-SOIC (0.209, 5.30mm Width). Package Tape & Reel (TR)embeds it. It is configured with Non-Invertedas an output. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 2V~3.6V volts. It is operating at a temperature of -40°C~85°C TA. The type of this D latch is D-Type. JK flip flop belongs to the 74LVXseries of FPGAs. A frequency of 90MHzshould not be exceeded by its output. A total of 1elements are present in it. It consumes 4μA of quiescent current without being affected by external factors. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. Power is provided by a 2.7V supply. This T flip flop has a capacitance of 4pF farads at the input. In this case, the D flip flop belongs to the LV/LV-A/LVX/Hfamily. Vsup reaches 3.6V, the maximal supply voltage. For normal operation, the supply voltage (Vsup) should be kept above 2V.
74LVX273SJX Features
Tape & Reel (TR) package
74LVX series
74LVX273SJX Applications
There are a lot of Rochester Electronics, LLC 74LVX273SJX Flip Flops applications.
- ESD performance
- Frequency division
- Computers
- Set-reset capability
- Patented noise
- Shift registers
- Modulo – n – counter
- QML qualified product
- Circuit Design
- Functionally equivalent to the MC10/100EL29
