74LVX74TTR
| Parameters | |
|---|---|
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVX |
| JESD-609 Code | e3/e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVX74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Clock Frequency | 85MHz |
| Propagation Delay | 18.5 ns |
| Quiescent Current | 2μA |
| Turn On Delay Time | 8.2 ns |
| Family | LV/LV-A/LVX/H |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 13.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Number of Output Lines | 1 |
| fmax-Min | 80 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 5mm |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVX74TTR Overview
14-TSSOP (0.173, 4.40mm Width)is the packaging method. It is contained within the Tape & Reel (TR)package. Currently, the output is configured to use Differential. JK flip flop uses Positive Edgeas the trigger. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a 2V~3.6Vvolt supply, it operates as follows. Currently, the operating temperature is -55°C~125°C TA. This D latch has the type D-Type. FPGAs belonging to the 74LVXseries contain this type of chip. In order for it to function properly, its output frequency should not exceed 85MHz. There are 14 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 74LVX74. A voltage of 2.7V is used to power it. Its input capacitance is 4pF farads. It is a member of the LV/LV-A/LVX/Hfamily of D flip flop. Electronic part Surface Mountis mounted in the way. 14pins are included in its design. The clock edge trigger type for this device is Positive Edge. The RS flip flops belongs to FF/Latches base part number. There is a 3.6Vmaximum supply voltage (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation. Despite its superior flexibility, it relies on 2 circuits to achieve it. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TAPE AND REEL. An electrical current of 3.3V volts is applied to it. It operates with 1 output lines. Despite external influences, it consumes 2μAof quiescent current.
74LVX74TTR Features
Tape & Reel (TR) package
74LVX series
14 pins
3.3V power supplies
74LVX74TTR Applications
There are a lot of STMicroelectronics 74LVX74TTR Flip Flops applications.
- Clock pulse
- High Performance Logic for test systems
- Storage Registers
- Pattern generators
- CMOS Process
- Data Synchronizers
- Memory
- Counters
- Safety Clamp
- Bus hold
