74VHC112MTC
| Parameters | |
|---|---|
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Weight | 173mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 74VHC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 3.3V |
| Base Part Number | 74VHC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Clock Frequency | 185MHz |
| Propagation Delay | 15 ns |
| Quiescent Current | 2μA |
| Turn On Delay Time | 5.1 ns |
| Family | AHC/VHC |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 8mA 8mA |
| Max I(ol) | 0.008 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 10.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 4pF |
| Number of Input Lines | 5 |
| Clock Edge Trigger Type | Negative Edge |
| Width | 4.4mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
74VHC112MTC Overview
16-TSSOP (0.173, 4.40mm Width)is the way it is packaged. Package Tubeembeds it. As configured, the output uses Differential. This trigger is configured to use Negative Edge. Surface Mountis positioned in the way of this electronic part. A voltage of 2V~5.5Vis required for its operation. A temperature of -40°C~85°C TAis used in the operation. A flip flop of this type is classified as a JK Type. FPGAs belonging to the 74VHCseries contain this type of chip. You should not exceed 185MHzin its output frequency. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. It is a member of the 74VHC112 family. Power is supplied from a voltage of 3.3V volts. The input capacitance of this T flip flop is 4pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. Devices in the AHC/VHCfamily are electronic devices. There is an electronic component mounted in the way of Surface Mount. As you can see from the design, it has pins with 16. This device exhibits a clock edge trigger type of Negative Edge. It is included in FF/Latches. The supply voltage (Vsup) should be kept above 2V for normal operation. To achieve this superior flexibility, 2 circuits are used. This D flip flop is well suited for RAIL based on its reliable performance. Currently, there are 5 input lines present. It consumes a total of 2μA quiescent current at any given time.
74VHC112MTC Features
Tube package
74VHC series
16 pins
74VHC112MTC Applications
There are a lot of ON Semiconductor 74VHC112MTC Flip Flops applications.
- ESD protection
- Data transfer
- Shift Registers
- Test & Measurement
- Matched Rise and Fall
- CMOS Process
- QML qualified product
- 2 – Bit synchronous counter
- Modulo – n – counter
- Frequency division
