74VHC112SJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74VHC |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Set(Preset) and Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Clock Frequency | 185MHz |
| Family | AHC/VHC |
| Current - Quiescent (Iq) | 2μA |
| Current - Output High, Low | 8mA 8mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 10.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 4pF |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74VHC112SJ Overview
It is packaged in the way of 16-SOIC (0.209, 5.30mm Width). It is contained within the Tubepackage. There is a Differentialoutput configured with it. The trigger it is configured with uses Negative Edge. There is an electrical part that is mounted in the way of Surface Mount. A voltage of 2V~5.5Vis required for its operation. It is operating at a temperature of -40°C~85°C TA. This D latch has the type JK Type. FPGAs belonging to the 74VHCseries contain this type of chip. A frequency of 185MHzshould not be exceeded by its output. The list contains 2 elements. There is 2μA quiescent consumption. Currently, there are 16 terminations. The D flip flop is powered by a voltage of 3.3V . This T flip flop has a capacitance of 4pF farads at the input. A device of this type belongs to the family of AHC/VHC. As soon as 5.5Vis reached, Vsup reaches its maximum value. The supply voltage (Vsup) should be maintained above 2V for normal operation.
74VHC112SJ Features
Tube package
74VHC series
74VHC112SJ Applications
There are a lot of Rochester Electronics, LLC 74VHC112SJ Flip Flops applications.
- Modulo – n – counter
- ESD protection
- Individual Asynchronous Resets
- Parallel data storage
- Divide a clock signal by 2 or 4
- Synchronous counter
- Differential Individual
- CMOS Process
- Patented noise
- Frequency division
