74VHC374FT
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74VHC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Ports | 2 |
| Clock Frequency | 120MHz |
| Family | AHC/VHC/H/U/V |
| Current - Quiescent (Iq) | 4μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 8mA 8mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10.1ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | RoHS Compliant |
74VHC374FT Overview
20-TSSOP (0.173, 4.40mm Width)is the way it is packaged. As part of the package Tape & Reel (TR), it is embedded. In the configuration, Tri-State, Non-Invertedis used as the output. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 2V~5.5V. It is operating at a temperature of -40°C~125°C TA. This logic flip flop is classified as type D-Type. This type of FPGA is a part of the 74VHC series. A frequency of 120MHzshould be the maximum output frequency. In total, there are 1 elements. There is a consumption of 4μAof quiescent energy. There have been 20 terminations. Power is supplied from a voltage of 5V volts. A JK flip flop with a 4pFfarad input capacitance is used here. It is a member of the AHC/VHC/H/U/Vfamily of D flip flop. It reaches the maximum supply voltage (Vsup) at 5.5V. Normal operation requires a supply voltage (Vsup) above 2V. The flip flop contains 2ports.
74VHC374FT Features
Tape & Reel (TR) package
74VHC series
74VHC374FT Applications
There are a lot of Toshiba Semiconductor and Storage 74VHC374FT Flip Flops applications.
- Safety Clamp
- Frequency division
- Balanced Propagation Delays
- Divide a clock signal by 2 or 4
- Patented noise
- Single Up Count-Control Line
- Guaranteed simultaneous switching noise level
- Asynchronous counter
- Bounce elimination switch
- Dynamic threshold performance
