74VHC374M
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74VHC |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Ports | 2 |
| Clock Frequency | 120MHz |
| Family | AHC/VHC |
| Current - Quiescent (Iq) | 4μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 8mA 8mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10.1ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Height Seated (Max) | 2.642mm |
| Width | 7.493mm |
| RoHS Status | ROHS3 Compliant |
74VHC374M Overview
It is packaged in the way of 20-SOIC (0.295, 7.50mm Width). D flip flop is embedded in the Tube package. T flip flop is configured with an output of Tri-State, Non-Inverted. There is a trigger configured with Positive Edge. Surface Mountis occupied by this electronic component. A voltage of 2V~5.5Vis used as the supply voltage. -40°C~85°C TAis the operating temperature. Logic flip flops of this type are classified as D-Type. In terms of FPGAs, it belongs to the 74VHC series. In order for it to function properly, its output frequency should not exceed 120MHz. There are 1 elements in it. As a result, it consumes 4μA quiescent current and is not affected by external forces. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is powered by a voltage of 3.3V . The input capacitance of this JK flip flopis 4pF farads. It belongs to the family of electronic devices known as AHC/VHC. Vsup reaches its maximum value at 5.5V. For normal operation, the supply voltage (Vsup) should be above 2V. The flip flop has 2embedded ports.
74VHC374M Features
Tube package
74VHC series
74VHC374M Applications
There are a lot of Rochester Electronics, LLC 74VHC374M Flip Flops applications.
- ATE
- Computing
- Latch-up performance
- Differential Individual
- 2 – Bit synchronous counter
- Digital electronics systems
- ESD protection
- Circuit Design
- Individual Asynchronous Resets
- Counters
