A2F200M3F-FG484
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 484-BGA |
| Surface Mount | YES |
| Number of Pins | 484 |
| Operating Temperature | 0°C~85°C TJ |
| Packaging | Tray |
| Series | SmartFusion® |
| JESD-609 Code | e0 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 484 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Subcategory | Field Programmable Gate Arrays |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 1mm |
| Frequency | 80MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | A2F200 |
| Number of Outputs | 94 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 1.575V |
| Supply Voltage-Min (Vsup) | 1.425V |
| Interface | EBI/EMI, Ethernet, I2C, SPI, UART, USART |
| Operating Supply Current | 2mA |
| Number of I/O | MCU - 41, FPGA - 94 |
| RAM Size | 64KB |
| Core Processor | ARM® Cortex®-M3 |
| Peripherals | DMA, POR, WDT |
| Connectivity | EBI/EMI, Ethernet, I2C, SPI, UART/USART |
| Architecture | MCU, FPGA |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Core Architecture | ARM |
| Number of Gates | 200000 |
| Number of Logic Blocks (LABs) | 8 |
| Primary Attributes | ProASIC®3 FPGA, 200K Gates, 4608 D-Flip-Flops |
| Flash Size | 256KB |
| Height Seated (Max) | 2.44mm |
| Length | 23mm |
| Width | 23mm |
| RoHS Status | Non-RoHS Compliant |
This SoC is built on ARM? Cortex?-M3 core processor(s).
ARM? Cortex?-M3 core processor(s) are used in the construction of this SoC.There is a 484-BGA package assigned to this system on a chip by the manufacturer.The 64KB RAM implementation of this SoC chip ensures efficient performance for users.In terms of internal architecture, this SoC design uses the MCU, FPGA method.It is a member of the SmartFusion? series.This SoC meaning should have an average operating temperature of 0°C~85°C TJ.A key point to note is that this SoC security combines ProASIC?3 FPGA, 200K Gates, 4608 D-Flip-Flops.This SoC system on a chip has been designed in a state-of-the-art Tray package.As a whole, this SoC part includes MCU - 41, FPGA - 94 I/Os.A 1.5V power supply is recommended.In the SoCs wireless, voltages above 1.575V are considered unsafe.It can feed on a power supply of at least 1.425V.You can reconfigure FIELD PROGRAMMABLE GATE ARRAY to meet your specific design needs.In total, there are 484 terminations, which is great for system on a chip.Furthermore, it has a remarkable system on a chip capability, much like other high-quality Field Programmable Gate Arrays.A SoC chip with 94 outputs is available.As for its flash size, it is 256KB.A search for A2F200 will result in system on chips that have similar specs and purposes.A wireless SoC that operates at a frequency of 80MHz is what the wireless SoC does.The SoC meaning is based on the core architecture of ARM.The computer SoC has 484 pins.
ARM? Cortex?-M3 processor.
64KB RAM.
Built on MCU, FPGA.
256KB extended flash.
Core Architecture: ARM
There are a lot of Microsemi Corporation
A2F200M3F-FG484 System On Chip (SoC) applications.
- Automotive
- Personal Computers
- AC drive control module
- Cyber security for critical applications in the aerospace
- Apple smart watch
- Multiprocessor system-on-chips (MPSoCs)
- Level
- RISC-V
- Industrial automation devices
- Communication interfaces ( I2C, SPI )
