A2F200M3F-PQ208I
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 208-BFQFP |
| Surface Mount | YES |
| Number of Pins | 208 |
| Operating Temperature | -40°C~100°C TJ |
| Packaging | Tray |
| Published | 2015 |
| Series | SmartFusion® |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Subcategory | Field Programmable Gate Arrays |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 0.5mm |
| Frequency | 80MHz |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Base Part Number | A2F200 |
| Number of Outputs | 66 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 1.575V |
| Supply Voltage-Min (Vsup) | 1.425V |
| Interface | EBI/EMI, Ethernet, I2C, SPI, UART, USART |
| Number of I/O | MCU - 22, FPGA - 66 |
| RAM Size | 64KB |
| Core Processor | ARM® Cortex®-M3 |
| Peripherals | DMA, POR, WDT |
| Connectivity | EBI/EMI, Ethernet, I2C, SPI, UART/USART |
| Architecture | MCU, FPGA |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Core Architecture | ARM |
| Number of Logic Blocks (LABs) | 8 |
| Primary Attributes | ProASIC®3 FPGA, 200K Gates, 4608 D-Flip-Flops |
| Number of Equivalent Gates | 200000 |
| Flash Size | 256KB |
| Height Seated (Max) | 4.1mm |
| RoHS Status | Non-RoHS Compliant |
This SoC is built on ARM? Cortex?-M3 core processor(s).
A core processor ARM? Cortex?-M3 is used to build this SoC.Manufacturer assigns package 208-BFQFP to this system on a chip.This SoC chip is equipped with 64KB RAM and guarantees reliable performance to the user.The SoC design uses MCU, FPGA architecture for its internal architecture.A system on chip SoC of this type belongs to the SmartFusion? series.It is expected that this SoC meaning will operate at -40°C~100°C TJ on average.There is one thing to note about this SoC security: it combines ProASIC?3 FPGA, 200K Gates, 4608 D-Flip-Flops.There is a state-of-the-art Tray package that houses this SoC system on a chip.In total, this SoC part has MCU - 22, FPGA - 66 I/Os.As a rule of thumb, it is advised to use a power supply with a value of 1.5V.For the SoCs wireless, a voltage higher than 1.575V is considered unsafe.As a minimum, the power supply of the SoC system on a chip needs to be 1.425V.Depending on your specific needs, FIELD PROGRAMMABLE GATE ARRAY can be re-configured.In total, there are 208 terminations, which is great for system on a chip.This system on a chip is just as capable as any other high-quality Field Programmable Gate Arrays.In order for this SoC chip to work properly, you can have 66 outputs.There is a flash of 256KB on it.Searching A2F200 will yield system on chips with similar specs and purposes.The wireless SoC works at a frequency of 80MHz.There are a number of features to this SoC meaning which are based on the core architecture of ARM.This is the version with 208 pins.
ARM? Cortex?-M3 processor.
64KB RAM.
Built on MCU, FPGA.
256KB extended flash.
Core Architecture: ARM
There are a lot of Microsemi Corporation
A2F200M3F-PQ208I System On Chip (SoC) applications.
- RISC-V
- Communication network-on-Chip (cNoC)
- Sports
- ARM
- Measurement tools
- Samsung galaxy gear
- Embedded systems
- Central alarm system
- Functional safety for critical applications in the aerospace
- String inverter
