A2F500M3G-PQ208I
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 208-BFQFP |
| Surface Mount | YES |
| Number of Pins | 208 |
| Operating Temperature | -40°C~100°C TJ |
| Packaging | Tray |
| Published | 2013 |
| Series | SmartFusion® |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| HTS Code | 8542.39.00.01 |
| Subcategory | Field Programmable Gate Arrays |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 0.5mm |
| Frequency | 80MHz |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Base Part Number | A2F500M3G |
| Number of Outputs | 66 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 1.575V |
| Power Supplies | 1.51.82.53.3V |
| Supply Voltage-Min (Vsup) | 1.425V |
| Interface | Ethernet, I2C, SPI, UART, USART |
| Number of I/O | MCU - 22, FPGA - 66 |
| RAM Size | 64KB |
| Core Processor | ARM® Cortex®-M3 |
| Peripherals | DMA, POR, WDT |
| Connectivity | Ethernet, I2C, SPI, UART/USART |
| Architecture | MCU, FPGA |
| Organization | 11520 CLBS, 500000 GATES |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Core Architecture | ARM |
| Number of Logic Blocks (LABs) | 24 |
| Primary Attributes | ProASIC®3 FPGA, 500K Gates, 11520 D-Flip-Flops |
| Number of Equivalent Gates | 500000 |
| Flash Size | 512KB |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | Non-RoHS Compliant |
This SoC is built on ARM? Cortex?-M3 core processor(s).
A core processor(s) ARM? Cortex?-M3 is integrated into this SoC.It has been assigned a package 208-BFQFP by its manufacturer for this system on a chip.Users will enjoy reliable performance with this SoC chip, which has implemented 64KB RAM.In terms of internal architecture, this SoC design uses the MCU, FPGA method.The SmartFusion? series contains this system on chip SoC.It is expected that this SoC meaning will operate at -40°C~100°C TJ on average.This SoC security combines ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops and that is something to note.Tray package houses this SoC system on a chip.This SoC part contains a total of MCU - 22, FPGA - 66 I/Os in total.It is advised to utilize a 1.5V power supply.There is no safe voltage for the SoCs wireless above 1.575V.This SoC system on a chip can run on a power supply that is at least 1.425V.Different designing requirements can be met with FIELD PROGRAMMABLE GATE ARRAY.As a result, there are 208 terminations in total, which does really benefit system on a chip.In addition, it boasts impressive system on a chipming capabilities, just like other high-quality Field Programmable Gate Arrays.A SoC chip like this can have 66 outputs.System on chip requires 1.51.82.53.3V power supplies.A 512KB flash can be seen on it.A search for A2F500M3G will result in system on chips that have similar specs and purposes.There is 80MHz frequency associated with the wireless SoC.Core architecture of ARM underpins the SoC meaning.208 pins are present on this computer SoC.
ARM? Cortex?-M3 processor.
64KB RAM.
Built on MCU, FPGA.
512KB extended flash.
Core Architecture: ARM
There are a lot of Microsemi Corporation
A2F500M3G-PQ208I System On Chip (SoC) applications.
- sequence controllers
- Robotics
- Digital Signal Processing
- Central inverter
- ARM
- CNC control
- USB hard disk enclosure
- POS Terminals
- Healthcare
- Vending machines
