A2F500M3G-PQG208
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 208-BFQFP |
| Surface Mount | YES |
| Number of Pins | 208 |
| Operating Temperature | 0°C~85°C TJ |
| Packaging | Tray |
| Series | SmartFusion® |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| Terminal Finish | Pure Matte Tin (Sn) |
| HTS Code | 8542.39.00.01 |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 0.5mm |
| Frequency | 80MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | A2F500M3G |
| Supply Voltage-Max (Vsup) | 1.575V |
| Supply Voltage-Min (Vsup) | 1.425V |
| Interface | Ethernet, I2C, SPI, UART, USART |
| Number of I/O | MCU - 22, FPGA - 66 |
| RAM Size | 64KB |
| Core Processor | ARM® Cortex®-M3 |
| Peripherals | DMA, POR, WDT |
| Connectivity | Ethernet, I2C, SPI, UART/USART |
| Architecture | MCU, FPGA |
| Organization | 11520 CLBS, 500000 GATES |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Core Architecture | ARM |
| Number of Logic Blocks (LABs) | 24 |
| Primary Attributes | ProASIC®3 FPGA, 500K Gates, 11520 D-Flip-Flops |
| Number of Equivalent Gates | 500000 |
| Flash Size | 512KB |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | RoHS Compliant |
This SoC is built on ARM? Cortex?-M3 core processor(s).
Based on the core processor(s) ARM? Cortex?-M3, this SoC has been developed.Its package is 208-BFQFP.Users will enjoy reliable performance with this SoC chip, which has implemented 64KB RAM.In terms of internal architecture, this SoC design uses the MCU, FPGA method.It is a member of the SmartFusion? series.It is recommended that this SoC meaning be operated at 0°C~85°C TJ on an average.This SoC security combines ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops and that is something to note.It comes in a state-of-the-art Tray package.This SoC part has a total of MCU - 22, FPGA - 66 I/Os.Use a power supply with a voltage of 1.5V if possible.For the SoCs wireless, a voltage higher than 1.575V is considered unsafe.In order to run it, it must be fed by at least 1.425V of power.It is possible to configure FIELD PROGRAMMABLE GATE ARRAY to meet specific needs during the design process.There are 208 terminations in total and that really benefits system on a chip.A 512KB flash can be seen on it.Searching A2F500M3G will bring up system on chips with similar specs and purposes.There is 80MHz frequency associated with the wireless SoC.In order to operate the SoC meaning, it must be based on the core architecture of ARM.The computer SoC has a pin count of 208.
ARM? Cortex?-M3 processor.
64KB RAM.
Built on MCU, FPGA.
512KB extended flash.
Core Architecture: ARM
There are a lot of Microsemi Corporation
A2F500M3G-PQG208 System On Chip (SoC) applications.
- USB hard disk enclosure
- Mouse
- sequence controllers
- Remote control
- Networked Media Encode/Decode
- Functional safety for critical applications in the aerospace
- Industrial sectors
- Automated sorting equipment
- Defense
- Central alarm system
