Parameters |
Radiation Hardening |
No |
REACH SVHC |
No SVHC |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
Factory Lead Time |
1 Week |
Lifecycle Status |
ACTIVE (Last Updated: 5 days ago) |
Contact Plating |
Gold |
Mount |
Through Hole |
Mounting Type |
Through Hole |
Package / Case |
16-DIP (0.300, 7.62mm) |
Number of Pins |
16 |
Weight |
951.693491mg |
Operating Temperature |
-55°C~125°C TA |
Packaging |
Tube |
Series |
4000B |
JESD-609 Code |
e4 |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
16 |
ECCN Code |
EAR99 |
Type |
D-Type |
Subcategory |
FF/Latches |
Technology |
CMOS |
Voltage - Supply |
3V~18V |
Terminal Position |
DUAL |
Supply Voltage |
5V |
Base Part Number |
CD40174 |
Function |
Master Reset |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Min (Vsup) |
3V |
Number of Channels |
4 |
Number of Circuits |
7 |
Load Capacitance |
50pF |
Power Dissipation |
500mW |
Output Current |
6.8mA |
Number of Bits |
6 |
Clock Frequency |
16MHz |
Propagation Delay |
300 ns |
Quiescent Current |
20μA |
Turn On Delay Time |
50 ns |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
4μA |
Current - Output High, Low |
6.8mA 6.8mA |
Max Propagation Delay @ V, Max CL |
100ns @ 15V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
5pF |
Number of Output Lines |
6 |
fmax-Min |
8 MHz |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
3500000Hz |
Height |
5.08mm |
Length |
19.3mm |
Width |
6.35mm |
Thickness |
3.9mm |
CD40174BE Overview
It is embeded in 16-DIP (0.300, 7.62mm) case. A package named Tubeincludes it. The output it is configured with uses Non-Inverted. It is configured with the trigger Positive Edge. There is an electronic component mounted in the way of Through Hole. The JK flip flop operates with an input voltage of 3V~18V volts. -55°C~125°C TAis the operating temperature. There is D-Type type of electronic flip flop associated with this device. In FPGA terms, D flip flop is a type of 4000Bseries FPGA. You should not exceed 16MHzin the output frequency of the device. There are 1 elements in it. As a result, it consumes 4μA quiescent current and is not affected by external forces. A total of 16terminations have been recorded. D latch belongs to the CD40174 family. It is powered by a voltage of 5V . Its input capacitance is 5pF farads. A part of the electronic system is mounted in the way of Through Hole. The 16pins are designed into the board. A Positive Edgeclock edge trigger is used in this device. This device is part of the FF/Latchesbase part number family. An electronic part with 6bits has been designed. For normal operation, the supply voltage (Vsup) should be above 3V. In order to achieve its superior flexibility, 7 circuits are used. With a current output of 6.8mA , it offers maximum design flexibility. It operates with 6 output lines. Despite external influences, it consumes 20μAof quiescent current. There are 4 channels available.
CD40174BE Features
Tube package
4000B series
16 pins
6 Bits
CD40174BE Applications
There are a lot of Texas Instruments CD40174BE Flip Flops applications.
- Counters
- Matched Rise and Fall
- Reduced system switching noise
- Supports Live Insertion
- Data transfer
- Storage registers
- Consumer
- Frequency Divider circuits
- Cold spare funcion
- Data storage