CD4027BE
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Number of Pins | 16 |
| Weight | 951.693491mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 4000B |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 3V~18V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Base Part Number | CD4027 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Operating Supply Voltage | 3.3V |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Power Dissipation | 500mW |
| Output Current | 6.8mA |
| Clock Frequency | 24MHz |
| Propagation Delay | 300 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 45 ns |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 6.8mA 6.8mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 90ns @ 15V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Power Supply Current-Max (ICC) | 0.06mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3500000Hz |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD4027BE Overview
It is embeded in 16-DIP (0.300, 7.62mm) case. D flip flop is embedded in the Tube package. Currently, the output is configured to use Differential. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Through Hole. The JK flip flop operates at 3V~18Vvolts. In this case, the operating temperature is -55°C~125°C TA. The type of this D latch is JK Type. It belongs to the 4000Bseries of FPGAs. Its output frequency should not exceed 24MHz. Despite external influences, it consumes 4μAof quiescent current. Terminations are 16. The object belongs to the CD4027 family. The D flip flop is powered by a voltage of 5V . Input capacitance of this device is 5pF farads. Electronic part Through Holeis mounted in the way. The 16pins are designed into the board. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. A normal operating voltage (Vsup) should remain above 3V. In order to achieve high efficiency, the supply voltage should be maintained at 3.3V. The output current of 6.8mA makes it feature maximum design flexibility. It consumes a total of 20μA quiescent current at any given time. A total of 2 channels are available.
CD4027BE Features
Tube package
4000B series
16 pins
CD4027BE Applications
There are a lot of Texas Instruments CD4027BE Flip Flops applications.
- Storage Registers
- Consumer
- Patented noise
- Buffered Clock
- Asynchronous counter
- Parallel data storage
- Guaranteed simultaneous switching noise level
- Frequency Divider circuits
- Set-reset capability
- Single Down Count-Control Line
