CD4027BNSR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Number of Pins | 16 |
| Weight | 200.686274mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Cut Tape (CT) |
| Series | 4000B |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 3V~18V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | CD4027 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Clock Frequency | 24MHz |
| Propagation Delay | 300 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 45 ns |
| Logic Function | AND, Flip-Flop |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 6.8mA 6.8mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 90ns @ 15V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Power Supply Current-Max (ICC) | 0.06mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3500000Hz |
| Height | 2mm |
| Length | 10.3mm |
| Width | 5.3mm |
| Thickness | 1.95mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD4027BNSR Overview
The flip flop is packaged in 16-SOIC (0.209, 5.30mm Width). D flip flop is embedded in the Cut Tape (CT) package. The output it is configured with uses Differential. There is a trigger configured with Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 3V~18V volts. In this case, the operating temperature is -55°C~125°C TA. The type of this D latch is JK Type. The 4000Bseries comprises this type of FPGA. You should not exceed 24MHzin its output frequency. During its operation, it consumes 4μA quiescent energy. A total of 16 terminations have been made. The object belongs to the CD4027 family. A voltage of 5V provides power to the D latch. The input capacitance of this T flip flop is 5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A part of the electronic system is mounted in the way of Surface Mount. This board is designed with 16pins on it. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is part of the FF/Latchesbase part number family. The supply voltage (Vsup) should be maintained above 3V for normal operation. The superior flexibility of this product is achieved by using 2 circuits. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. It consumes a total of 20μA quiescent current at any given time.
CD4027BNSR Features
Cut Tape (CT) package
4000B series
16 pins
CD4027BNSR Applications
There are a lot of Texas Instruments CD4027BNSR Flip Flops applications.
- Convert a momentary switch to a toggle switch
- Set-reset capability
- Parallel data storage
- Balanced Propagation Delays
- Common Clocks
- Communications
- Matched Rise and Fall
- ESD protection
- Digital electronics systems
- Consumer
