CD74AC112M
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 day ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74AC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Base Part Number | 74AC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3/5V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 100MHz |
| Propagation Delay | 129 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 2.6 ns |
| Family | AC |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 10.3ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74AC112M Overview
It is packaged in the way of 16-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. As configured, the output uses Differential. The trigger it is configured with uses Negative Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 1.5V~5.5V volts. In the operating environment, the temperature is -55°C~125°C TA. The type of this D latch is JK Type. JK flip flop is a part of the 74ACseries of FPGAs. You should not exceed 100MHzin the output frequency of the device. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74AC112family includes it. Power is supplied from a voltage of 3.3V volts. There is 10pF input capacitance for this T flip flop. A device of this type belongs to the family of AC. It is mounted by the way of Surface Mount. 16pins are included in its design. Its clock edge trigger type is Negative Edge. The part is included in FF/Latches. It reaches the maximum supply voltage (Vsup) at 5.5V. The D latch operates on 3.3/5V volts. With a current output of 24mA , it offers maximum design flexibility. There is a consumption of 4μAof quiescent current from it. 2is the number of channels.
CD74AC112M Features
Tube package
74AC series
16 pins
3.3/5V power supplies
CD74AC112M Applications
There are a lot of Texas Instruments CD74AC112M Flip Flops applications.
- Bus hold
- Parallel data storage
- Counters
- Automotive
- Single Up Count-Control Line
- Buffered Clock
- Registers
- Clock pulse
- Reduced system switching noise
- Consumer
