CD74ACT109M96E4
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ACT |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74ACT109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Operating Supply Voltage | 5V |
| Polarity | Non-Inverting |
| Power Supplies | 5V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 100MHz |
| Propagation Delay | 10.3 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 2.6 ns |
| Family | ACT |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 10.3ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74ACT109M96E4 Overview
As a result, it is packaged as 16-SOIC (0.154, 3.90mm Width). D flip flop is embedded in the Tape & Reel (TR) package. T flip flop is configured with an output of Differential. JK flip flop uses Positive Edgeas the trigger. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 4.5V~5.5V volts. Temperature is set to -55°C~125°C TA. JK Typedescribes this flip flop. JK flip flop is a part of the 74ACTseries of FPGAs. You should not exceed 100MHzin its output frequency. A total of 16terminations have been recorded. You can search similar parts based on 74ACT109. A voltage of 5V is used to power it. A JK flip flop with a 10pFfarad input capacitance is used here. ACTis the family of this D flip flop. This electronic part is mounted in the way of Surface Mount. 16pins are included in its design. The clock edge trigger type for this device is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The superior flexibility of this circuit is achieved by using 2 circuits. In view of its reliability, this D flip flop is a good fit for TR. A power supply of 5Vis required to operate it. A high level of efficiency can be achieved by maintaining the supply voltage at 5V. It offers maximum design flexibility with its output current of 24mA. 4μAquiescent current consumed.
CD74ACT109M96E4 Features
Tape & Reel (TR) package
74ACT series
16 pins
5V power supplies
CD74ACT109M96E4 Applications
There are a lot of Texas Instruments CD74ACT109M96E4 Flip Flops applications.
- Computers
- Asynchronous counter
- Digital electronics systems
- Dynamic threshold performance
- ESD performance
- Individual Asynchronous Resets
- QML qualified product
- Circuit Design
- EMI reduction circuitry
- Convert a momentary switch to a toggle switch
