CD74ACT273E
| Parameters | |
|---|---|
| Clock Frequency | 85MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 8μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 13.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 10pF |
| Height Seated (Max) | 5.33mm |
| Width | 7.62mm |
| RoHS Status | Non-RoHS Compliant |
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDIP-T20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
CD74ACT273E Overview
The package is in the form of 20-DIP (0.300, 7.62mm). The package Tubecontains it. T flip flop is configured with an output of Non-Inverted. Positive Edgeis the trigger it is configured with. There is an electric part mounted in the way of Through Hole. With a supply voltage of 4.5V~5.5V volts, it operates. A temperature of -55°C~125°C TAis considered to be the operating temperature. This logic flip flop is classified as type D-Type. The FPGA belongs to the 74ACT series. This D flip flop should not have a frequency greater than 85MHz. A total of 1 elements are present. As a result, it consumes 8μA quiescent current. Currently, there are 20 terminations. It is powered from a supply voltage of 5V. The input capacitance of this JK flip flopis 10pF farads. A device of this type belongs to the family of ACT. As soon as 5.5Vis reached, Vsup reaches its maximum value. The supply voltage (Vsup) should be maintained above 4.5V for normal operation.
CD74ACT273E Features
Tube package
74ACT series
CD74ACT273E Applications
There are a lot of Rochester Electronics, LLC CD74ACT273E Flip Flops applications.
- Shift Registers
- Automotive
- Consumer
- Reduced system switching noise
- Digital electronics systems
- Divide a clock signal by 2 or 4
- Storage Registers
- Dynamic threshold performance
- QML qualified product
- Common Clocks
