CD74HC112E
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Number of Pins | 16 |
| Weight | 951.693491mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Supply Voltage | 4.5V |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 270 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Prop. Delay@Nom-Sup | 53 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC112E Overview
It is embeded in 16-DIP (0.300, 7.62mm) case. D flip flop is included in the Tubepackage. There is a Differentialoutput configured with it. It is configured with a trigger that uses a value of Negative Edge. Through Holeis in the way of this electric part. It operates with a supply voltage of 2V~6V. -55°C~125°C TAis the operating temperature. The type of this D latch is JK Type. In this case, it is a type of FPGA belonging to the 74HC series. A frequency of 60MHzshould not be exceeded by its output. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. If you search by 74HC112, you will find similar parts. An input voltage of 4.5Vpowers the D latch. The input capacitance of this T flip flop is 10pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. HC/UHis the family of this D flip flop. The electronic part is mounted in the way of Through Hole. Basically, it is designed with a set of 16 pins. The clock edge trigger type for this device is Negative Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. Vsup reaches its maximum value at 6V. Normal operation requires a supply voltage (Vsup) above 2V. It offers maximum design flexibility with its output current of 5.2mA. Despite external influences, it consumes 4μAof quiescent current. The number of channels is growing strong/weak: 2.
CD74HC112E Features
Tube package
74HC series
16 pins
CD74HC112E Applications
There are a lot of Texas Instruments CD74HC112E Flip Flops applications.
- Parallel data storage
- Supports Live Insertion
- Shift registers
- CMOS Process
- Matched Rise and Fall
- Power down protection
- Count Modes
- High Performance Logic for test systems
- Shift Registers
- Divide a clock signal by 2 or 4
