CD74HC112MT
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Termination | SMD/SMT |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 175 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Prop. Delay@Nom-Sup | 53 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC112MT Overview
16-SOIC (0.154, 3.90mm Width)is the packaging method. Package Tape & Reel (TR)embeds it. As configured, the output uses Differential. The trigger configured with it uses Negative Edge. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates at 2V~6Vvolts. In this case, the operating temperature is -55°C~125°C TA. The type of this D latch is JK Type. JK flip flop belongs to the 74HCseries of FPGAs. A frequency of 60MHzshould not be exceeded by its output. It has been determined that there have been 16 terminations. Members of the 74HC112family make up this object. The D flip flop is powered by a voltage of 4.5V . JK flip flop input capacitance is 10pF farads. A device of this type belongs to the family of HC/UH. Electronic part Surface Mountis mounted in the way. This board has 16 pins. Its clock edge trigger type is Negative Edge. The part is included in FF/Latches. Vsup reaches 6V, the maximal supply voltage. Normally, the supply voltage (Vsup) should be kept above 2V. Due to its superior flexibility, it uses 2 circuits. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. The 5.2mA output current allows it to be designed with the greatest amount of flexibility. Despite external influences, it consumes 4μAof quiescent current.
CD74HC112MT Features
Tape & Reel (TR) package
74HC series
16 pins
CD74HC112MT Applications
There are a lot of Texas Instruments CD74HC112MT Flip Flops applications.
- Set-reset capability
- Supports Live Insertion
- Guaranteed simultaneous switching noise level
- Shift Registers
- Latch
- Clock pulse
- Frequency Dividers
- Computing
- Control circuits
- ESD performance
