CD74HC112PW
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 day ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Weight | 61.887009mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latch |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 270 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Prop. Delay@Nom-Sup | 53 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC112PW Overview
The flip flop is packaged in 16-TSSOP (0.173, 4.40mm Width). D flip flop is embedded in the Tube package. As configured, the output uses Differential. This trigger is configured to use Negative Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 2V~6V volts. A temperature of -55°C~125°C TAis considered to be the operating temperature. The type of this D latch is JK Type. This type of FPGA is a part of the 74HC series. You should not exceed 60MHzin the output frequency of the device. It has been determined that there have been 16 terminations. The 74HC112family includes it. Power is provided by a 4.5V supply. The input capacitance of this JK flip flopis 10pF farads. An electronic device belonging to the family HC/UHcan be found here. A part of the electronic system is mounted in the way of Surface Mount. With its 16pins, it is designed to work with most electronic flip flops. This device's clock edge trigger type is Negative Edge. The RS flip flops belongs to FF/Latch base part number. There is a 6Vmaximum supply voltage (Vsup). Normally, the supply voltage (Vsup) should be kept above 2V. The superior flexibility of this product is achieved by using 2 circuits. With an output current of 5.2mA, this device offers maximum design flexibility. It consumes a total of 4μA quiescent current at any given time.
CD74HC112PW Features
Tube package
74HC series
16 pins
CD74HC112PW Applications
There are a lot of Texas Instruments CD74HC112PW Flip Flops applications.
- Latch-up performance
- Count Modes
- Clock pulse
- Power down protection
- Single Down Count-Control Line
- ESD protection
- Consumer
- Frequency Dividers
- QML qualified product
- Data transfer
