CD74HC73E
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Through Hole |
| Mounting Type | Through Hole |
| Package / Case | 14-DIP (0.300, 7.62mm) |
| Number of Pins | 14 |
| Weight | 927.99329mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Supply Voltage | 4.5V |
| Base Part Number | 74HC73 |
| Function | Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 160 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 13 ns |
| Family | HC/UH |
| Logic Function | Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 28ns @ 6V, 50pF |
| Prop. Delay@Nom-Sup | 40 ns |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 5.08mm |
| Length | 19.3mm |
| Width | 6.35mm |
| Thickness | 3.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC73E Overview
14-DIP (0.300, 7.62mm)is the packaging method. A package named Tubeincludes it. As configured, the output uses Differential. It is configured with the trigger Negative Edge. There is an electrical part that is mounted in the way of Through Hole. The JK flip flop operates at a voltage of 2V~6V. A temperature of -55°C~125°C TAis considered to be the operating temperature. It belongs to the type JK Typeof flip flops. It belongs to the 74HCseries of FPGAs. In order for it to function properly, its output frequency should not exceed 60MHz. There are 14 terminations,JK flip flop belongs to 74HC73 family. An input voltage of 4.5Vpowers the D latch. The input capacitance of this T flip flop is 10pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. This D flip flop belongs to the family of HC/UH. Through Hole mounts this electronic component. A total of 14pins are provided on this board. A Negative Edgeclock edge trigger is used in this device. The RS flip flops belongs to FF/Latches base part number. 6Vis the maximum supply voltage (Vsup). The supply voltage (Vsup) should be kept above 2V for normal operation. The 5.2mA output current allows it to be designed with the greatest amount of flexibility. There is a consumption of 4μAof quiescent current from it. Currently, there are 2 channels available.
CD74HC73E Features
Tube package
74HC series
14 pins
CD74HC73E Applications
There are a lot of Texas Instruments CD74HC73E Flip Flops applications.
- Patented noise
- Cold spare funcion
- Frequency division
- Dynamic threshold performance
- Data Synchronizers
- Automotive
- Registers
- Memory
- ESCC
- High Performance Logic for test systems
