Parameters |
Mounting Type |
Through Hole |
Package / Case |
16-DIP (0.300, 7.62mm) |
Surface Mount |
NO |
Operating Temperature |
-55°C~125°C TA |
Packaging |
Tube |
Series |
74HCT |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
16 |
Type |
JK Type |
Technology |
CMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Supply Voltage |
5V |
Function |
Set(Preset) and Reset |
Qualification Status |
COMMERCIAL |
Output Type |
Differential |
Number of Elements |
2 |
Supply Voltage-Max (Vsup) |
5.5V |
Supply Voltage-Min (Vsup) |
4.5V |
Clock Frequency |
54MHz |
Family |
HCT |
Current - Quiescent (Iq) |
4μA |
Current - Output High, Low |
4mA 4mA |
Output Polarity |
COMPLEMENTARY |
Number of Bits per Element |
1 |
Max Propagation Delay @ V, Max CL |
40ns @ 4.5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
10pF |
Propagation Delay (tpd) |
50 ns |
fmax-Min |
54 MHz |
RoHS Status |
Non-RoHS Compliant |
CD74HCT109E Overview
The flip flop is packaged in a case of 16-DIP (0.300, 7.62mm). You can find it in the Tubepackage. It is configured with Differentialas an output. This trigger is configured to use Positive Edge. Through Holeis in the way of this electric part. The JK flip flop operates at 4.5V~5.5Vvolts. Temperature is set to -55°C~125°C TA. There is JK Type type of electronic flip flop associated with this device. JK flip flop belongs to the 74HCTseries of FPGAs. In order for it to function properly, its output frequency should not exceed 54MHz. In total, there are 2 elements. This process consumes 4μA quiescents. Currently, there are 16 terminations. An input voltage of 5Vpowers the D latch. Its input capacitance is 10pF farads. The electronic device belongs to the HCTfamily. The maximal supply voltage (Vsup) reaches 5.5V. For normal operation, the supply voltage (Vsup) should be above 4.5V.
CD74HCT109E Features
Tube package
74HCT series
CD74HCT109E Applications
There are a lot of Rochester Electronics, LLC CD74HCT109E Flip Flops applications.
- Frequency division
- 2 – Bit synchronous counter
- Single Up Count-Control Line
- ATE
- CMOS Process
- High Performance Logic for test systems
- Load Control
- Power down protection
- EMI reduction circuitry
- Differential Individual