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CD74HCT273E

4.5V~5.5V 50MHz D-Type Flip Flop 8μA 74HCT Series 20-DIP (0.300, 7.62mm)


  • Manufacturer: Rochester Electronics, LLC
  • Nocochips NO: 699-CD74HCT273E
  • Package: 20-DIP (0.300, 7.62mm)
  • Datasheet: PDF
  • Stock: 576
  • Description: 4.5V~5.5V 50MHz D-Type Flip Flop 8μA 74HCT Series 20-DIP (0.300, 7.62mm)(Kg)

Details

Tags

Parameters
Mounting Type Through Hole
Package / Case 20-DIP (0.300, 7.62mm)
Supplier Device Package 20-PDIP
Operating Temperature -55°C~125°C TA
Packaging Tube
Series 74HCT
Part Status Obsolete
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Type D-Type
Voltage - Supply 4.5V~5.5V
Function Master Reset
Output Type Non-Inverted
Number of Elements 1
Clock Frequency 50MHz
Current - Quiescent (Iq) 8μA
Current - Output High, Low 4mA 4mA
Number of Bits per Element 8
Max Propagation Delay @ V, Max CL 30ns @ 4.5V, 50pF
Trigger Type Positive Edge
Input Capacitance 10pF
RoHS Status Non-RoHS Compliant

CD74HCT273E Overview


The flip flop is packaged in a case of 20-DIP (0.300, 7.62mm). D flip flop is embedded in the Tube package. The output it is configured with uses Non-Inverted. This trigger uses the value Positive Edge. Through Holeis in the way of this electric part. A voltage of 4.5V~5.5Vis used as the supply voltage. A temperature of -55°C~125°C TAis considered to be the operating temperature. The type of this D latch is D-Type. The FPGA belongs to the 74HCT series. You should not exceed 50MHzin the output frequency of the device. There are 1 elements in it. It consumes 8μA of quiescent current without being affected by external factors. JK flip flop input capacitance is 10pF farads.

CD74HCT273E Features


Tube package
74HCT series

CD74HCT273E Applications


There are a lot of Rochester Electronics, LLC CD74HCT273E Flip Flops applications.

  • Single Up Count-Control Line
  • High Performance Logic for test systems
  • Shift Registers
  • Supports Live Insertion
  • 2 – Bit synchronous counter
  • Reduced system switching noise
  • Count Modes
  • Counters
  • Pattern generators
  • Individual Asynchronous Resets

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