Parameters |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
84 |
Packaging |
Bulk |
JESD-609 Code |
e0 |
Number of Terminations |
84 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
70°C |
Min Operating Temperature |
0°C |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Reach Compliance Code |
not_compliant |
Pin Count |
84 |
Qualification Status |
Not Qualified |
Operating Supply Voltage |
5V |
Temperature Grade |
COMMERCIAL |
Max Supply Voltage |
5.25V |
Min Supply Voltage |
4.75V |
Number of I/O |
69 |
Memory Type |
FLASH |
Clock Frequency |
80MHz |
Propagation Delay |
12 ns |
Number of Logic Blocks (LABs) |
4 |
Output Function |
MACROCELL |
Number of Macro Cells |
64 |
JTAG BST |
NO |
Number of Dedicated Inputs |
1 |
In-System Programmable |
YES |
Height Seated (Max) |
5.08mm |
Length |
29.3116mm |
Width |
29.3116mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
CY7C373I-100JC Overview
There are 64 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.The item is enclosed in a PLCC package.The device is programmed with 69 I/O ports.The termination of a device is set to [0].The terminal position of this electrical part is QUAD, which serves as an important access point for passengers or freight.It is powered from a supply voltage of 5V.It is a part of family [0].Ideally, the chip should be packaged by Bulk.Chips are programmed with 84 pins.In order to maintain high efficiency, the supply voltage should be maintained at [0].For storing data, it is recommended to use [0].In this case, it is mounted by Surface Mount.The device is designed with pins [0].In this case, the maximum supply voltage is 5.25V.It is powered by 4.75Vas its minimum supply voltage.In order to operate properly, the operating temperature should be higher than 0°C.Temperatures should be lower than 70°C when operating.In total, it contains 4 logic blocks (LABs).To detect the status of input signals, there are 1dedicated inputs.The clock frequency of the device should not exceed 80MHz.
CY7C373I-100JC Features
PLCC package
69 I/Os
84 pin count
84 pins
4 logic blocks (LABs)
CY7C373I-100JC Applications
There are a lot of Cypress Semiconductor CY7C373I-100JC CPLDs applications.
- DMA control
- Dedicated input registers
- Code converters
- Portable digital devices
- Protection relays
- Wireless Infrastructure Base Band Unit and Remote Radio Unit
- Field programmable gate
- Wide Vin Industrial low power SMPS
- TIMERS/COUNTERS
- Digital designs