DM74AS874WM
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 24-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74AS |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH CLEAR |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Number of Ports | 2 |
| Clock Frequency | 80MHz |
| Family | AS |
| Current - Quiescent (Iq) | 133mA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 15mA 48mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 4 |
| Max Propagation Delay @ V, Max CL | 10.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 10.5 ns |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
DM74AS874WM Overview
As a result, it is packaged as 24-SOIC (0.295, 7.50mm Width). It is included in the package Tube. Currently, the output is configured to use Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 4.5V~5.5V volts. It is at 0°C~70°C TAdegrees Celsius that the system is operating. D-Typeis the type of this D latch. It is a type of FPGA belonging to the 74AS series. You should not exceed 80MHzin the output frequency of the device. There are 2 elements in it. This process consumes 133mA quiescents. There are 24 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. An input voltage of 5Vpowers the D latch. It is a member of the ASfamily of D flip flop. As soon as Vsup reaches 5.5V, the maximum supply voltage is reached. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Furthermore, it has WITH CLEARas a characteristic.
DM74AS874WM Features
Tube package
74AS series
DM74AS874WM Applications
There are a lot of Rochester Electronics, LLC DM74AS874WM Flip Flops applications.
- Computers
- Balanced Propagation Delays
- Functionally equivalent to the MC10/100EL29
- Modulo – n – counter
- Single Down Count-Control Line
- Counters
- Latch-up performance
- Load Control
- Data transfer
- Communications
