EPM5032DC-20
| Parameters | |
|---|---|
| Surface Mount | NO |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 28 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | MACROCELLS INTERCONNECTED BY PIA; 1 LAB; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | DUAL |
| Terminal Form | THROUGH-HOLE |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 28 |
| JESD-30 Code | R-GDIP-T28 |
| Number of Outputs | 16 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 16 |
| Clock Frequency | 62.5MHz |
| Propagation Delay | 20 ns |
| Architecture | PAL-TYPE |
| Number of Inputs | 24 |
| Organization | 7 DEDICATED INPUTS, 16 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Dedicated Inputs | 7 |
| Number of Product Terms | 320 |
| RoHS Status | Non-RoHS Compliant |
EPM5032DC-20 Overview
The device is programmed with 16 I/O ports.There are 28 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.This electrical part is wired with a terminal position of DUAL.A voltage of 5Vprovides power to the device.The part is included in Programmable Logic Devices.In this chip, the 28pins are programmed.When using this device, MACROCELLS INTERCONNECTED BY PIA; 1 LAB; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCKcan also be found.This device runs on 5Vvolts of electricity.In this case, the maximum supply voltage (Vsup) reaches 5.25V.It has 7dedicated inputs for detecting input signals.It should be possible for Vsup to exceed 4.75Vat the supply voltage.Ideally, its clock frequency should not exceed 62.5MHz.Programmable logic types can be divided into UV PLD.This device has 16outputs configured.It is associated with 320product terms.Keeping the operating temperature below 70°C is recommended.The device employs 24 inputs.
EPM5032DC-20 Features
16 I/Os
28 pin count
5V power supplies
16 outputs
EPM5032DC-20 Applications
There are a lot of Altera EPM5032DC-20 CPLDs applications.
- DMA control
- Field programmable gate
- Parity generators
- I/O expansion
- Pattern recognition
- State machine control
- Multiple DIP Switch Replacement
- INTERRUPT SYSTEM
- Configurable Addressing of I/O Boards
- PLC analog input modules
