EPM5064JC-1
| Parameters | |
|---|---|
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 44 |
| JESD-30 Code | S-CQCC-J44 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 28 |
| Clock Frequency | 50MHz |
| Propagation Delay | 40 ns |
| Organization | 7 DEDICATED INPUTS, 28 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 7 |
| In-System Programmable | NO |
| Height Seated (Max) | 4.57mm |
| Length | 16.51mm |
| Width | 16.51mm |
| RoHS Status | Non-RoHS Compliant |
| Surface Mount | YES |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 44 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
EPM5064JC-1 Overview
The mobile phone network has 64 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).As a result, it has 28 I/O ports programmed.It is programmed to terminate devices at [0].The terminal position of this electrical part is QUAD, which serves as an important access point for passengers or freight.Power is supplied by a voltage of 5V volts.This part is in the family [0].It is equipped with 44 pin count.When using this device, LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCKcan also be found.It runs on 5Vvolts of power.In this case, the maximum supply voltage (Vsup) is 5.25V.A total of 7dedicated inputs are available for the purpose of detecting input signals.It is recommended that the supply voltage (Vsup) be greater than 4.75V.It is recommended that the clock frequency not exceed 50MHz.Programmable logic types can be divided into UV PLD.Keep the operating temperature below 70°C.
EPM5064JC-1 Features
28 I/Os
44 pin count
5V power supplies
EPM5064JC-1 Applications
There are a lot of Altera EPM5064JC-1 CPLDs applications.
- D/T registers and latches
- Timing control
- Digital multiplexers
- State machine control
- Cross-Matrix Switch
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- Handheld digital devices
- Address decoding
- White goods (Washing, Cold, Aircon ,...)
- Software-Driven Hardware Configuration
