EPM5130JC-1
| Parameters | |
|---|---|
| Surface Mount | YES |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 84 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 84 |
| JESD-30 Code | S-CQCC-J84 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 48 |
| Clock Frequency | 50MHz |
| Propagation Delay | 40 ns |
| Organization | 19 DEDICATED INPUTS, 48 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 19 |
| In-System Programmable | NO |
| Height Seated (Max) | 5.08mm |
| Length | 29.21mm |
| Width | 29.21mm |
| RoHS Status | Non-RoHS Compliant |
EPM5130JC-1 Overview
There are 128 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).The device has 48inputs and outputs.84terminations have been programmed into the device.This electrical part has a terminal position of [0], which serves as an important point of access for passengers and freight.The power supply voltage is 5V.There is a part included in Programmable Logic Devices.It is programmed with 84 pins.Additionally, this device is capable of displaying [0].It runs on 5Vvolts of power.Vsup reaches 5.25Vas the maximum supply voltage.There are 19 dedicated inputs used to detect the status of input signals.Voltage supply (Vsup) should be higher than 4.75V.The clock frequency should not exceed 50MHz.A programmable logic type can be categorized as UV PLD.The operating temperature should be kept below 70°C.
EPM5130JC-1 Features
48 I/Os
84 pin count
5V power supplies
EPM5130JC-1 Applications
There are a lot of Altera EPM5130JC-1 CPLDs applications.
- Programmable polarity
- Portable digital devices
- Preset swapping
- Multiple DIP Switch Replacement
- LED Lighting systems
- Synchronous or asynchronous mode
- Digital designs
- POWER-SAVING MODES
- D/T registers and latches
- Digital multiplexers
