EPM5130JC
| Parameters | |
|---|---|
| Surface Mount | YES |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Number of Terminations | 84 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 84 |
| JESD-30 Code | S-CQCC-J84 |
| Qualification Status | Not Qualified |
| Operating Temperature (Max) | 70°C |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 5V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 48 |
| Clock Frequency | 33.3MHz |
| Propagation Delay | 55 ns |
| Organization | 19 DEDICATED INPUTS, 48 I/O |
| Programmable Logic Type | UV PLD |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 19 |
| In-System Programmable | NO |
| Height Seated (Max) | 5.08mm |
| Length | 29.21mm |
| Width | 29.21mm |
| RoHS Status | Non-RoHS Compliant |
EPM5130JC Overview
The mobile phone network has 128 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).There are 48 I/Os programmed in it.It is programmed that device terminations will be 84 .This electrical part has a terminal position of [0], which serves as an important point of access for passengers and freight.The power source is powered by 5Vvolts.This part is included in Programmable Logic Devices.The chip is programmed with 84 pins.If you use this device, you will also find [0].Currently, it is powered by 5Vsources.Supply voltage (Vsup) reaches a maximum of 5.25V.There are 19 dedicated inputs used to detect the status of input signals.Vsup (supply voltage) must be greater than 4.75V.A frequency of 33.3MHzshould not be exceeded by its clock.In programmable logic, a type of logic can be categorized as UV PLD.Keeping the operating temperature below 70°C is recommended.
EPM5130JC Features
48 I/Os
84 pin count
5V power supplies
EPM5130JC Applications
There are a lot of Altera EPM5130JC CPLDs applications.
- PLC analog input modules
- Voltage level translation
- State machine control
- DMA control
- I/O PORTS (MCU MODULE)
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Complex programmable logic devices
- TIMERS/COUNTERS
- Cross-Matrix Switch
- Pattern recognition
