EPM7064AEFC100-10N
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Package / Case | FBGA |
| Number of Pins | 100 |
| Published | 1998 |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 100 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Pin Count | 100 |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 68 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Frequency (Max) | 222.2MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 1250 |
| Number of Programmable I/O | 68 |
| Number of Logic Blocks (LABs) | 4 |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 1.7mm |
| Length | 11mm |
| Width | 11mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
EPM7064AEFC100-10N Overview
A mobile phone network consists of 64macro cells, which are radio coverage cells served by a high-power cell site (tower, antenna or mast).The item is packaged with FBGA.There are 68 I/Os programmed in it.Terminations of devices are set to [0].This electrical part has a terminal position of BOTTOMand is connected to the ground.A voltage of 3.3Vprovides power to the device.The part is included in Programmable Logic Devices.A chip with 100pins is programmed.It is possible to construct digital circuits using 1250gates, which are devices that serve as building blocks.For high efficiency, the supply voltage should be maintained at [0].Data storage is performed using [0].Surface Mountis used to mount this electronic component.100pins are included in its design.It operates with the maximal supply voltage of 3.6V.The minimal supply voltage is 3V.There are 68 programmable I/Os in this system.There is 125MHz frequency that can be achieved.Operating temperatures should be higher than 0°C.Ideally, the operating temperature should be below 70°C.The system consists of 4 logic blocks (LABs).It is recommended that the maximum frequency be less than 222.2MHz.There are several types of programmable logic that can be categorized as EE PLD.
EPM7064AEFC100-10N Features
FBGA package
68 I/Os
100 pin count
100 pins
4 logic blocks (LABs)
EPM7064AEFC100-10N Applications
There are a lot of Altera EPM7064AEFC100-10N CPLDs applications.
- D/T registers and latches
- State machine design
- Complex programmable logic devices
- Software Configuration of Add-In Boards
- Custom state machines
- Digital systems
- Multiple Clock Source Selection
- ToR/Aggregation/Core Switch and Router
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Code converters
