Parameters |
Factory Lead Time |
1 Week |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
44 |
Published |
1998 |
JESD-609 Code |
e3 |
Pbfree Code |
yes |
Moisture Sensitivity Level (MSL) |
3 |
Number of Terminations |
44 |
ECCN Code |
EAR99 |
Terminal Finish |
Matte Tin (Sn) - annealed |
Max Operating Temperature |
85°C |
Min Operating Temperature |
-40°C |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
245 |
Supply Voltage |
3.3V |
Frequency |
166.67MHz |
Time@Peak Reflow Temperature-Max (s) |
40 |
Pin Count |
44 |
Operating Supply Voltage |
3.3V |
Temperature Grade |
INDUSTRIAL |
Max Supply Voltage |
3.6V |
Min Supply Voltage |
3V |
Number of I/O |
36 |
Memory Type |
EEPROM |
Propagation Delay |
7.5 ns |
Turn On Delay Time |
7.5 ns |
Frequency (Max) |
222.2MHz |
Programmable Logic Type |
EE PLD |
Number of Gates |
1250 |
Number of Programmable I/O |
36 |
Number of Logic Blocks (LABs) |
4 |
Speed Grade |
7 |
Output Function |
MACROCELL |
Number of Macro Cells |
64 |
JTAG BST |
YES |
In-System Programmable |
YES |
Length |
16.5862mm |
Width |
16.5862mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
EPM7064AELI44-7N Overview
There are 64 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).The product is contained in a PLCC package.It is equipped with 36I/O ports.44terminations are programmed into the device.As the terminal position of this electrical part is [0], it serves as an important access point for passengers and freight.The power supply voltage is 3.3V.The part belongs to Programmable Logic Devices family.In this chip, the 44pins are programmed.As a building block for digital circuits, there are 1250gates.In order to maintain high efficiency, the supply voltage should be maintained at [0].In order to store data, EEPROMis used.A Surface Mountis mounted on this electronic component.The device is designed with pins [0].It operates with the maximal supply voltage of 3.6V.The minimal supply voltage is 3V.Currently, there are 36 Programmable I/Os available.There is a maximum frequency of 166.67MHz.The operating temperature should be higher than -40°C.Ideally, the operating temperature should be below 85°C.The program consists of 4 logic blocks (LABs).There should be a lower maximum frequency than 222.2MHz.It is possible to classify programmable logic as EE PLD.
EPM7064AELI44-7N Features
PLCC package
36 I/Os
44 pin count
44 pins
4 logic blocks (LABs)
EPM7064AELI44-7N Applications
There are a lot of Altera EPM7064AELI44-7N CPLDs applications.
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- Discrete logic functions
- State machine control
- Multiple Clock Source Selection
- Power Meter SMPS
- Handheld digital devices
- State machine design
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- Dedicated input registers
- Software-driven hardware configuration