Parameters |
Propagation Delay |
7.5 ns |
Architecture |
PLA-TYPE |
Number of Inputs |
68 |
Number of Gates |
1250 |
Output Function |
MACROCELL |
Number of Macro Cells |
64 |
JTAG BST |
YES |
Voltage Supply - Internal |
3V~3.6V |
Delay Time tpd(1) Max |
7.5ns |
Number of Logic Elements/Blocks |
4 |
Height Seated (Max) |
1.27mm |
RoHS Status |
RoHS Compliant |
Factory Lead Time |
1 Week |
Mounting Type |
Surface Mount |
Package / Case |
100-TQFP |
Surface Mount |
YES |
Operating Temperature |
0°C~70°C TA |
Packaging |
Tray |
Series |
MAX® 7000A |
JESD-609 Code |
e3 |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
100 |
ECCN Code |
EAR99 |
Terminal Finish |
Matte Tin (Sn) |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
3.3V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
40 |
Base Part Number |
EPM7064 |
JESD-30 Code |
S-PQFP-G100 |
Number of Outputs |
68 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
3.6V |
Power Supplies |
2.5/3.33.3V |
Supply Voltage-Min (Vsup) |
3V |
Programmable Type |
In System Programmable |
Number of I/O |
68 |
Clock Frequency |
135.1MHz |
EPM7064AETC100-7N Overview
Currently, there are 64 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.The item is enclosed in a 100-TQFP package.The device has 68inputs and outputs.The termination of a device is set to [0].Its terminal position is QUAD.It is powered by a voltage of 3.3V volts.This part is in the family [0].Trayis the packaging method.To ensure its reliability, the operating temperature is set to [0].It is mounted in the way of Surface Mount.It is a type of FPGA belonging to the MAX? 7000A series.The EPM7064contains its related parts.It is possible to construct digital circuits using 1250gates, which are devices that serve as building blocks.There are 4 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.A total of 2.5/3.33.3V power supplies are needed to run it.3.6Vis the maximum supply voltage (Vsup).The supply voltage (Vsup) should be greater than 3V.The clock frequency should not exceed 135.1MHz.The device is configured with an output of [0].It uses 68inputs in order to function.
EPM7064AETC100-7N Features
100-TQFP package
68 I/Os
The operating temperature of 0°C~70°C TA
2.5/3.33.3V power supplies
68 outputs
EPM7064AETC100-7N Applications
There are a lot of Intel EPM7064AETC100-7N CPLDs applications.
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- Complex programmable logic devices
- INTERRUPT SYSTEM
- Dedicated input registers
- D/T registers and latches
- LED Lighting systems
- Boolean function generators
- Address decoders
- Discrete logic functions
- Page register