EPM7064SLC84-10
| Parameters | |
|---|---|
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 5.25V |
| Min Supply Voltage | 4.75V |
| Number of I/O | 68 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Frequency (Max) | 175.4MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 1250 |
| Number of Programmable I/O | 68 |
| Number of Logic Blocks (LABs) | 4 |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height | 3.81mm |
| Length | 29.31mm |
| Width | 29.31mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
| Mount | Surface Mount |
| Package / Case | PLCC |
| Number of Pins | 84 |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Moisture Sensitivity Level (MSL) | 2 |
| Number of Terminations | 84 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 84 |
| Operating Supply Voltage | 5V |
EPM7064SLC84-10 Overview
There are 64 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is part of the PLCC package.In this case, there are 68 I/Os programmed.The device is programmed with 84 terminations.There is a QUADterminal position on the electrical part in question.There is 5V voltage supply for this device.The part belongs to Programmable Logic Devices family.A chip with 84pins is programmed.It is also characterized by CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V.In digital circuits, 1250gates serve as building blocks.High efficiency requires the supply voltage to be maintained at [0].It is adopted to store data in [0].It is mounted by Surface Mount.There are 84pins on it.A maximum supply voltage of 5.25Vis used in its operation.It operates with the minimal supply voltage of 4.75V.There are 68 Programmable I/Os.There can be 125MHz frequency achieved.Operating temperatures should be higher than 0°C.A temperature less than 70°Cshould be used for operation.It consists of 4 logic blocks (LABs).Maximum frequency should be less than 175.4MHz.A programmable logic type is categorized as EE PLD.
EPM7064SLC84-10 Features
PLCC package
68 I/Os
84 pin count
84 pins
4 logic blocks (LABs)
EPM7064SLC84-10 Applications
There are a lot of Altera EPM7064SLC84-10 CPLDs applications.
- POWER-SAVING MODES
- TIMERS/COUNTERS
- Software-driven hardware configuration
- Programmable power management
- Multiple Clock Source Selection
- Parity generators
- Complex programmable logic devices
- Portable digital devices
- Battery operated portable devices
- Cross-Matrix Switch
