EPM7064SLC84-7N
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 84-LCC (J-Lead) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | MAX® 7000S |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 84 |
| ECCN Code | EAR99 |
| Terminal Finish | Matte Tin (Sn) |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Reach Compliance Code | compliant |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | EPM7064 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 3.3/55V |
| Programmable Type | In System Programmable |
| Number of I/O | 68 |
| Clock Frequency | 166.7MHz |
| Propagation Delay | 7.5 ns |
| Number of Gates | 1250 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | NO |
| Voltage Supply - Internal | 4.75V~5.25V |
| Delay Time tpd(1) Max | 7.5ns |
| Number of Logic Elements/Blocks | 4 |
| Height Seated (Max) | 5.08mm |
| Length | 29.3116mm |
| Width | 29.3116mm |
| RoHS Status | RoHS Compliant |
EPM7064SLC84-7N Overview
Currently, there are 64 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.It is contained in package [0].The device has 68inputs and outputs.There is a 84terminations set on devices.QUADis the terminal position of this electrical part.A voltage of 5V is used as the power supply for this device.It is a part of family [0].It is recommended to package the chip by Tray.To ensure reliability, the device operates at a temperature of [0].It is mounted in the way of Surface Mount.The FPGA belongs to the MAX? 7000S series.This device can also display [0].You can find its related parts in the [0].1250gates are devices that serve as building blocks for digital circuits.There are a total of 4 logic elements or blocks.In order for the device to operate, it requires 3.3/55V power supplies.In this case, the maximum supply voltage (Vsup) is 5.25V.The clock frequency of this device should not exceed 166.7MHz.
EPM7064SLC84-7N Features
84-LCC (J-Lead) package
68 I/Os
The operating temperature of 0°C~70°C TA
3.3/55V power supplies
EPM7064SLC84-7N Applications
There are a lot of Intel EPM7064SLC84-7N CPLDs applications.
- Power automation
- STANDARD SERIAL INTERFACE UART
- USB Bus
- D/T registers and latches
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- DDC INTERFACE
- INTERRUPT SYSTEM
- I/O PORTS (MCU MODULE)
- Timing control
- Digital systems
