Parameters |
Factory Lead Time |
1 Week |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
84 |
Published |
1998 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Moisture Sensitivity Level (MSL) |
2 |
Number of Terminations |
84 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
85°C |
Min Operating Temperature |
-40°C |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
220 |
Supply Voltage |
5V |
Frequency |
166.7MHz |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
84 |
Power Supplies |
3.3/55V |
Temperature Grade |
INDUSTRIAL |
Max Supply Voltage |
3.6V |
Min Supply Voltage |
3V |
Number of I/O |
68 |
Memory Type |
EEPROM |
Propagation Delay |
7.5 ns |
Turn On Delay Time |
7.5 ns |
Frequency (Max) |
175.4MHz |
Programmable Logic Type |
EE PLD |
Number of Gates |
1250 |
Number of Programmable I/O |
68 |
Number of Logic Blocks (LABs) |
4 |
Speed Grade |
7 |
Output Function |
MACROCELL |
Number of Macro Cells |
64 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
5.08mm |
Length |
29.3116mm |
Width |
29.3116mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
Lead Free |
Contains Lead |
EPM7064SLI84-7 Overview
This network has 64macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).It is contained in package [0].There are 68 I/Os programmed in it.The device is programmed with 84 terminations.This electrical part has a terminal position of QUADand is connected to the ground.The power source is powered by 5Vvolts.The part is included in Programmable Logic Devices.Chips are programmed with 84 pins.1250gates are used to construct digital circuits.It is adopted to store data in [0].It is mounted by Surface Mount.There are 84 pins on the device.There is a maximum supply voltage of 3.6V.A minimum supply voltage of 3V is required for this device to operate.In order for the device to operate, it requires 3.3/55V power supplies.A total of 68programmable I/Os are available.This frequency can be achieved at 166.7MHz.In order to operate, the temperature should be higher than -40°C.The operating temperature should be lower than 85°C.In its simplest form, it consists of 4 logic blocks (LABs).If the maximal frequency is less than [0], it should be lower than that.In programmable logic, a type of logic can be categorized as EE PLD.
EPM7064SLI84-7 Features
PLCC package
68 I/Os
84 pin count
84 pins
3.3/55V power supplies
4 logic blocks (LABs)
EPM7064SLI84-7 Applications
There are a lot of Altera EPM7064SLI84-7 CPLDs applications.
- TIMERS/COUNTERS
- Multiple DIP Switch Replacement
- State machine control
- Address decoding
- Boolean function generators
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- Handheld digital devices
- Digital systems
- Programmable power management
- Protection relays