Parameters |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
84 |
Published |
1998 |
JESD-609 Code |
e0 |
Pbfree Code |
yes |
Part Status |
Discontinued |
Number of Terminations |
84 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
70°C |
Min Operating Temperature |
0°C |
Additional Feature |
CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
245 |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Frequency |
166.7MHz |
Time@Peak Reflow Temperature-Max (s) |
40 |
Pin Count |
84 |
Qualification Status |
Not Qualified |
Operating Supply Voltage |
5V |
Temperature Grade |
COMMERCIAL |
Max Supply Voltage |
5.25V |
Min Supply Voltage |
4.75V |
Number of I/O |
68 |
Memory Type |
EEPROM |
Propagation Delay |
7.5 ns |
Frequency (Max) |
125MHz |
Programmable Logic Type |
EE PLD |
Number of Gates |
1800 |
Number of Programmable I/O |
64 |
Number of Logic Blocks (LABs) |
6 |
Output Function |
MACROCELL |
Number of Macro Cells |
96 |
JTAG BST |
NO |
In-System Programmable |
NO |
Height Seated (Max) |
5.08mm |
RoHS Status |
RoHS Compliant |
Lead Free |
Contains Lead |
EPM7096LC84-7 Overview
A mobile phone network consists of 96macro cells, which are radio coverage cells served by a high-power cell site (tower, antenna or mast).It is embedded in the PLCC package.The device is programmed with 68 I/Os.There is a 84terminations set on devices.QUADis the terminal position of this electrical part.A voltage of 5V is used as the power supply for this device.This part is included in Programmable Logic Devices.It is programmed with 84 pins.This device also displays [0].In digital circuits, there are 1800gates, which act as a basic building block.In order to maintain high efficiency, the supply voltage should be maintained at [0].In this case, EEPROMwill be used to store the data.The electronic component is mounted by Surface Mount.84pins are included in its design.This device operates at a voltage of 5.25V when the maximum supply voltage is applied.Despite its minimal supply voltage of [0], it is capable of operating.There are 64 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. There is a maximum frequency of 166.7MHz.Operating temperatures should be higher than 0°C.Temperatures should be lower than 70°C when operating.In its simplest form, it consists of 6 logic blocks (LABs).It is recommended that the maximal frequency be less than 0.A programmable logic type is classified as EE PLD.
EPM7096LC84-7 Features
PLCC package
68 I/Os
84 pin count
84 pins
6 logic blocks (LABs)
EPM7096LC84-7 Applications
There are a lot of Altera EPM7096LC84-7 CPLDs applications.
- Handheld digital devices
- Pattern recognition
- DMA control
- High speed graphics processing
- Random logic replacement
- Battery operated portable devices
- Power up sequencing
- Multiple Clock Source Selection
- I2C BUS INTERFACE
- Programmable power management