Parameters |
Factory Lead Time |
1 Week |
Mount |
Surface Mount |
Package / Case |
FBGA |
Number of Pins |
100 |
Published |
2014 |
JESD-609 Code |
e1 |
Pbfree Code |
yes |
Moisture Sensitivity Level (MSL) |
3 |
Number of Terminations |
100 |
ECCN Code |
3A991 |
Terminal Finish |
TIN SILVER COPPER |
Max Operating Temperature |
85°C |
Min Operating Temperature |
-40°C |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
3.3V |
Frequency |
166.67MHz |
Time@Peak Reflow Temperature-Max (s) |
40 |
Pin Count |
100 |
Operating Supply Voltage |
3.3V |
Temperature Grade |
INDUSTRIAL |
Max Supply Voltage |
3.6V |
Min Supply Voltage |
3V |
Number of I/O |
84 |
Memory Type |
EEPROM |
Propagation Delay |
7.5 ns |
Turn On Delay Time |
7.5 ns |
Frequency (Max) |
192.3MHz |
Programmable Logic Type |
EE PLD |
Number of Gates |
2500 |
Number of Programmable I/O |
84 |
Number of Logic Blocks (LABs) |
8 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
Height |
1.1mm |
Length |
11mm |
Width |
11mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
EPM7128AEFI100-7N Overview
There are 128 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).The item is packaged with FBGA.There are 84 I/Os programmed in it.The termination of a device is set to [0].This electrical part is wired with a terminal position of BOTTOM.It is powered by a voltage of 3.3V volts.It is programmed with 100 pins.In digital circuits, there are 2500gates, which act as a basic building block.A high level of efficiency can be achieved by maintaining the supply voltage at [0].EEPROM is adopted for storing data.It is mounted by Surface Mount.A total of 100pins are provided on this board.It operates with the maximal supply voltage of 3.6V.It is powered by 3Vas its minimum supply voltage.A total of 84 Programmable I/Os are available.You can achieve 166.67MHzfrequencies.Operating temperatures should be higher than -40°C.There should be a temperature below 85°Cat the time of operation.The logic block consists of 8 l logic blocks (LABs).It is recommended that the maximal frequency be lower than 192.3MHz.In programmable logic, a type of logic can be categorized as EE PLD.
EPM7128AEFI100-7N Features
FBGA package
84 I/Os
100 pin count
100 pins
8 logic blocks (LABs)
EPM7128AEFI100-7N Applications
There are a lot of Altera EPM7128AEFI100-7N CPLDs applications.
- Wireless Infrastructure Base Band Unit and Remote Radio Unit
- Wide Vin Industrial low power SMPS
- State machine control
- Code converters
- Digital multiplexers
- PULSE WIDTH MODULATION (PWM)
- Synchronous or asynchronous mode
- DMA control
- ToR/Aggregation/Core Switch and Router
- Bootloaders for FPGAs