EPM7128AELC84-10
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Package / Case | PLCC |
| Number of Pins | 84 |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Moisture Sensitivity Level (MSL) | 2 |
| Number of Terminations | 84 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1.27mm |
| Reach Compliance Code | unknown |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 84 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 68 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Frequency (Max) | 192.3MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 68 |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height | 3.81mm |
| Length | 29.31mm |
| Width | 29.31mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
EPM7128AELC84-10 Overview
There are 128 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.PLCCis the package in which it resides.It is equipped with 68I/O ports.84terminations are programmed into the device.This electrical component has a terminal position of 0.There is 3.3V voltage supply for this device.The part is included in Programmable Logic Devices.With 84pins programmed, the chip is ready to use.If you use this device, you will also find [0].2500gates are devices that serve as building blocks for digital circuits.For high efficiency, the supply voltage should be maintained at [0].For data storage, EEPROMis adopted.Surface Mountis used to mount this electronic component.There are 84 pins on the device.It operates at a maximum supply voltage of 3.6V volts.The minimal supply voltage is 3V.There are 68 programmable I/Os in this system.There is 125MHz frequency that can be achieved.Ideally, the operating temperature should be greater than 0°C.A temperature below 70°Cshould be used as the operating temperature.In its simplest form, it consists of 8 logic blocks (LABs).If the maximal frequency is less than [0], it should be lower than that.Types of programmable logic are divided into EE PLD.
EPM7128AELC84-10 Features
PLCC package
68 I/Os
84 pin count
84 pins
8 logic blocks (LABs)
EPM7128AELC84-10 Applications
There are a lot of Altera EPM7128AELC84-10 CPLDs applications.
- Digital systems
- Digital multiplexers
- Wide Vin Industrial low power SMPS
- Programmable polarity
- Software Configuration of Add-In Boards
- STANDARD SERIAL INTERFACE UART
- Page register
- Interface bridging
- Discrete logic functions
- Custom state machines
